Our core competence lies in the development of HDL-based IP-cores for FPGA implementation resulting in a very short product development cycle for the client. We have designed, developed, tested and verified various FPGA IP cores that are targeted for Xilinx devices. These IP cores are successfully implemented at various customer locations. These IPs can also be made available for other FPGA devices and ASIC*standard cell libraries flow according to customer needs.
We can also develop new custom built IP cores and customize the available cores as per the customers needs to meet their requirements.
Given below is a list of available IP cores and brief description about each of them:
IP Core |
Brief Description |
|
|
JPEG 2000 Encoder |
JPEG2000 Image compression Core compliant with JPEG2000 standard. |
10/100 Mbit Ethernet MAC |
IEEE 802.3-802.3u compliant core. |
RS Encoder
RS Decoder |
G.709 compliant core with symbol width of 8 bits. Fully synchronous and pipelined design with shortened code support. |
Viterbi decoder |
Industry standard constraint length 7, rate = ½, (G0, G1) = (171, 133) Viterbi decoder with parallel architecture and fully synchronous design. |
Generic Framing Procedure (GFP) |
This core implements the ITU-T G.7041 communication standard. The core operates in Frame mapped GFP (GFP – F) mode. |
Direct Digital Synthesizer (DDS) |
This IP core digitally creates arbitrary waveforms and frequencies from a single, fixed source frequency. |
The IP Cores under development are:
- IMBE Vocoder on DSP.
- JPEG 2000 with NTSC/PAL interface.
For enquiries or questions on IP cores, please contact sales@vxldesign.com
*ASIC flow provided through a partner of VXL. |
